1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Slew Rate Definitions for Single-Ended Input Signals
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate be-
tween the last crossing of VREF and the first crossing of VIH(AC)min. Setup (tIS and tDS)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VREF and the first crossing of VIL(AC)max
.
Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate be-
tween the last crossing of VIL(DC)max and the first crossing of VREF. Hold (tIH and tDH)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VIH(DC)min and the first crossing of VREF (see Figure 21 (page 55)).
Table 29: Single-Ended Input Slew Rate Definition
Input Slew Rates
(Linear Signals)
Measured
Input
Edge
From
To
Calculation
Setup
Rising
VREF
VIH(AC)min
VIL(AC)max
VREF
V
V
V
V
- V
IH(AC)min
REF
ǻTRS
se
Falling
Rising
Falling
VREF
- V
REF
IL(AC)max
ǻTFS
se
Hold
VIL(DC)max
- V
REF
IL(DC)max
ǻTFH
se
VIH(DC)min
VREF
- V
IH(DC)min
REF
ǻTRSH
se
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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54
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