1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications
Input/Output Capacitance
Table 7: DDR3 Input/Output Capacitance
Note 1 applies to the entire table
800
1066
1333
1600
1866
2133
Capacitance
Parameters
Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes
CK and CK#
CCK
CDCK
CIO
0.8
0
1.6
0.15
3.0
0.8
0
1.6
0.15
2.7
0.8
0
1.4
0.15
2.5
0.8
0
1.4
0.15
2.3
0.8
0
1.3
0.15
2.2
0.8
0
1.3
pF
ΔC: CK to CK#
0.15 pF
Single-end I/O:
DQ, DM
1.5
1.5
1.5
1.5
1.5
1.5
2.1
2.1
pF
pF
2
3
Differential I/O:
DQS, DQS#,
TDQS, TDQS#
CIO
1.5
0
3.0
0.2
1.5
0
2.7
0.2
1.5
0
2.5
1.5
0
2.3
1.5
0
2.2
1.5
0
ΔC: DQS to
DQS#, TDQS,
TDQS#
CDDQS
0.15
0.15
0.15
0.15 pF
3
ΔC: DQ to DQS
CDIO
CI
–0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3
0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2
pF
pF
4
5
Inputs (CTRL,
CMD, ADDR)
ΔC: CTRL to CK
CDI_CTRL –0.5 0.3 –0.5 0.3 –0.4 0.2 –0.4 0.2 –0.4 0.2 –0.4 0.2
pF
pF
6
7
ΔC: CMD_ADDR CDI_CMD_ –0.5 0.5 –0.5 0.5 –0.4 0.4 –0.4 0.4 –0.4 0.4 –0.4 0.4
to CK
ADDR
ZQ pin capaci-
tance
CZQ
CRE
–
–
3.0
3.0
–
–
3.0
3.0
–
–
3.0
3.0
–
–
3.0
3.0
–
–
3.0
3.0
–
–
3.0
3.0
pF
pF
Reset pin capaci-
tance
1. VDD = 1.5V 0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) = 0.5 ×
DDQ, VOUT = 0.1V (peak-to-peak).
Notes:
V
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. CDIO = CIO(DQ) - 0.5 × (CIO(DQS) + CIO(DQS#)).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =
A[n:0], BA[2:0].
6. CDI_CTRL = CI(CTRL) - 0.5 × (CCK(CK) + CCK(CK#)).
7. CDI_CMD_ADDR = CI(CMD_ADDR) - 0.5 × (CCK(CK) + CCK(CK#)).
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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31
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