1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)
Symbol
Type
Description
Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are
referenced to VREFDQ
DQ0, DQ1, DQ2,
DQ3, DQ4, DQ5,
DQ6, DQ7
I/O
.
DQS, DQS#
I/O
Data strobe: Output with read data. Edge-aligned with read data. Input with write
data. Center-aligned to write data.
TDQS, TDQS#
Output
Termination data strobe: Applies to the x8 configuration only. When TDQS is
enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resist-
ance.
VDD
Supply
Supply
Power supply: 1.5V 0.075V.
VDDQ
DQ power supply: 1.5V 0.075V. Isolated on the device for improved noise immuni-
ty.
VREFCA
VREFDQ
Supply
Supply
Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS
VSSQ
ZQ
Supply
Supply
Ground.
DQ ground: Isolated on the device for improved noise immunity.
External reference ball for output drive calibration: This ball is tied to an
Reference
external 240Ω resistor (RZQ), which is tied to VSSQ
.
NC
NF
–
–
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
No function: When configured as a x4 device, these balls are NF. When configured as
a x8 device, these balls are defined as TDQS#, DQ[7:4].
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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