1Gb: x4, x8, x16 DDR3 SDRAM
READ Operation
READ Operation
READ bursts are initiated with a READ command. The starting column and bank ad-
dresses are provided with the READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address is
available READ latency (RL) clocks later. RL is defined as the sum of posted CAS additive
latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programma-
ble in the mode register via the MRS command. Each subsequent data-out element is
valid nominally at the next positive or negative clock edge (that is, at the next crossing
of CK and CK#). Figure 68 shows an example of RL based on a CL setting of 8 and an AL
setting of ±.
Figure 68: READ Latency
T0
T7
T8
T9
T10
T11
T12
T12
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank a,
Col n
Address
CL = 8, AL = 0
DQS, DQS#
DQ
DO
n
Indicates break
in time scale
Transitioning Data
Don’t Care
1. DO n = data-out from column n.
Notes:
2. Subsequent elements of data-out appear in the programmed order following DO n.
DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state on
DQS and HIGH state on DQS# is known as the READ preamble (tRPRE). The LOW state
on DQS and the HIGH state on DQS#, coincident with the last data-out element, is
known as the READ postamble (tRPST). Upon completion of a burst, assuming no other
commands have been initiated, the DQ goes High-Z. A detailed explanation of tDQSQ
(valid data-out skew), tQH (data-out window hold), and the valid data window are de-
picted in Figure 09 (page 160). A detailed explanation of tDQSCK (DQS transition skew
to CK) is also depicted in Figure 09 (page 160).
Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued tCCD cycles after the first READ command. This is shown for BL8 in Figure 69
(page 161). If BC4 is enabled, tCCD must still be met, which will cause a gap in the data
output, as shown in Figure 0± (page 161). Nonconsecutive READ data is reflected in
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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