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MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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1Gb: x4, x8, x16 DDR3 SDRAM  
ZQ CALIBRATION Operation  
ZQ CALIBRATION Operation  
The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON  
and ODT values (RTT) over process, voltage, and temperature, provided a dedicated  
24±Ω (±1ꢀ) external resistor is connected from the DRAM’s ZQ ball to VSSQ  
)
.
DDR3 SDRAM require a longer time to calibrate RON and ODT at power-up initialization  
and self refresh exit, and a relatively shorter time to perform periodic calibrations.  
DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An example  
of ZQ calibration timing is shown below.  
All banks must be precharged and tRP must be met before ZQCL or ZQCS commands  
can be issued to the DRAM. No other activities (other than issuing another ZQCL or  
ZQCS command) can be performed on the DRAM channel by the controller for the du-  
ration of tZQinit or tZQoper. The quiet time on the DRAM channel helps accurately cali-  
brate RON and ODT. After DRAM calibration is achieved, the DRAM should disable the  
ZQ ball’s current consumption path to reduce power.  
ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.  
Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.  
In dual-rank systems that share the ZQ resistor between devices, the controller must not  
enable overlap of tZQinit, tZQoper, or tZQCS between ranks.  
Figure 65: ZQ CALIBRATION Timing (ZQCL and ZQCS)  
T0  
T1  
Ta0  
Ta1  
Ta2  
Ta3  
Tb0  
Tb1  
Tc0  
Tc1  
Tc2  
CK#  
CK  
Command  
Address  
A10  
ZQCL  
NOP  
NOP  
NOP  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
ZQCS  
NOP  
NOP  
NOP  
Valid  
Valid  
Valid  
CKE  
1
2
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
1
2
ODT  
Activ-  
ities  
DQ  
3
High-Z  
Activities  
3
High-Z  
tZQCS  
tZQinit or tZQoper  
Indicates break  
in time scale  
Don’t Care  
1. CKE must be continuously registered HIGH during the calibration procedure.  
2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.  
3. All devices connected to the DQ bus should be High-Z during calibration.  
Notes:  
PDF: 09005aef826aa906  
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
156  
‹ 2006 Micron Technology, Inc. All rights reserved.  
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