1Gb: x4, x8, x16 DDR3 SDRAM
MODE REGISTER SET (MRS) Command
MPR Read Predefined Pattern
The predetermined read calibration pattern is a fixed pattern of ±, 1, ±, 1, ±, 1, ±, 1. The
following is an example of using the read out predetermined read calibration pattern.
The example is to perform multiple reads from the multipurpose register to do system
level read timing calibration based on the predetermined and standardized pattern.
The following protocol outlines the steps used to perform the read calibration:
1. Precharge all banks
2. After tRP is satisfied, set MRS, MR3[2] = 1 and MR3[1:±] = ±±. This redirects all sub-
sequent reads and loads the predefined pattern into the MPR. As soon as tMRD
and tMOD are satisfied, the MPR is available
3. Data WRITE operations are not allowed until the MPR returns to the normal
DRAM state
4. Issue a read with burst order information (all other address pins are “Don’t Care”):
• A[1:±] = ±± (data burst order is fixed starting at nibble)
• A2 = ± (for BL8, burst order is fixed as ±, 1, 2, 3, 4, 5, 6, 0)
• A12 = 1 (use BL8)
5. After RL = AL + CL, the DRAM bursts out the predefined read calibration pattern
(±, 1, ±, 1, ±, 1, ±, 1)
6. The memory controller repeats the calibration reads until read data capture at
memory controller is optimized
0. After the last MPR READ burst and after tMPRR has been satisfied, issue MRS,
MR3[2] = ±, and MR3[1:±] = “Don’t Care” to the normal DRAM state. All subse-
quent read and write accesses will be regular reads and writes from/to the DRAM
array
8. When tMRD and tMOD are satisfied from the last MRS, the regular DRAM com-
mands (such as activate a memory bank for regular read or write access) are per-
mitted
MODE REGISTER SET (MRS) Command
The mode registers are loaded via inputs BA[2:±], A[13:±]. BA[2:±] determine which
mode register is programmed:
• BA2 = ±, BA1 = ±, BA± = ± for MR±
• BA2 = ±, BA1 = ±, BA± = 1 for MR1
• BA2 = ±, BA1 = 1, BA± = ± for MR2
• BA2 = ±, BA1 = 1, BA± = 1 for MR3
The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (tRP is satisfied and no data bursts are in progress). The controller
must wait the specified time tMRD before initiating a subsequent operation such as an
ACTIVATE command (see Figure 51 (page 136)). There is also a restriction after issuing
an MRS command with regard to when the updated functions become available. This
parameter is specified by tMOD. Both tMRD and tMOD parameters are shown in Fig-
ure 51 (page 136) and Figure 52 (page 130). Violating either of these requirements will
result in unspecified operation.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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