1Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 3 (MR3)
fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ
latencies and AC timings applicable, provided the DLL is locked as required.
MPR addressing for a valid MPR read is as follows:
• A[1:±] must be set to ±± as the burst order is fixed per nibble
• A2 selects the burst order:
– BL8, A2 is set to ±, and the burst order is fixed to ±, 1, 2, 3, 4, 5, 6, 0
• For burst chop 4 cases, the burst order is switched on the nibble base along with the
following:
– A2 = ±; burst order = ±, 1, 2, 3
– A2 = 1; burst order = 4, 5, 6, 0
• Burst order bit ± (the first bit) is assigned to LSB, and burst order bit 0 (the last bit) is
assigned to MSB
• A[9:3] are a “Don’t Care”
• A1± is a “Don’t Care”
• A11 is a “Don’t Care”
• A12: Selects burst chop mode on-the-fly, if enabled within MR±
• A13 is a “Don’t Care”
• BA[2:±] are a “Don’t Care”
MPR Register Address Definitions and Bursting Order
The MPR currently supports a single data format. This data format is a predefined read
pattern for system calibration. The predefined pattern is always a repeating ±–1 bit pat-
tern.
Examples of the different types of predefined READ pattern bursts are shown in the fol-
lowing figures.
Table 78: MPR Readouts and Burst Order Bit Mapping
Burst
Length
Read
A[2:0]
MR3[2] MR3[1:0]
Function
Burst Order and Data Pattern
1
00
READ predefined pattern
for system calibration
BL8
BC4
BC4
000
000
100
Burst order: 0, 1, 2, 3, 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1
Burst order: 0, 1, 2, 3
Predefined pattern: 0, 1, 0, 1
Burst order: 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1
1
1
01
10
RFU
RFU
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
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1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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