欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT250QL01GABA8ESF0AITES 参数 Datasheet PDF下载

MT250QL01GABA8ESF0AITES图片预览
型号: MT250QL01GABA8ESF0AITES
PDF下载: 下载PDF文件 查看货源
内容描述: [3V, Multiple I/O, 4KB, 32KB, 64KB, Sector Erase]
分类和应用:
文件页数/大小: 97 页 / 1038 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT250QL01GABA8ESF0AITES的Datasheet PDF文件第24页浏览型号MT250QL01GABA8ESF0AITES的Datasheet PDF文件第25页浏览型号MT250QL01GABA8ESF0AITES的Datasheet PDF文件第26页浏览型号MT250QL01GABA8ESF0AITES的Datasheet PDF文件第27页浏览型号MT250QL01GABA8ESF0AITES的Datasheet PDF文件第29页浏览型号MT250QL01GABA8ESF0AITES的Datasheet PDF文件第30页浏览型号MT250QL01GABA8ESF0AITES的Datasheet PDF文件第31页浏览型号MT250QL01GABA8ESF0AITES的Datasheet PDF文件第32页  
256Mb, 3V Multiple I/O Serial Flash Memory  
Nonvolatile Configuration Register  
Nonvolatile Configuration Register  
This register is read from and written to using the READ NONVOLATILE CONFIGURA-  
TION REGISTER and the WRITE NONVOLATILE CONFIGURATION REGISTER com-  
mands, respectively. A register download is executed during power-on or after reset,  
overwriting the internal configuration register settings that determine device behavior.  
Table 7: Nonvolatile Configuration Register  
Bit Name  
Settings  
Description  
Notes  
15:12 Number of  
0000 = Identical to 1111  
Sets the number of dummy clock cycles subse-  
quent to all FAST READ commands.  
(See the Command Set Table for default setting  
values.)  
1
dummy clock cy- 0001 = 1  
cles  
0010 = 2  
1101 = 13  
1110 = 14  
1111 = Default  
11:9 XIP mode at  
power-on reset  
000 = XIP: Fast read  
Enables the device to operate in the selected XIP  
mode immediately after power-on reset.  
001 = XIP: Dual output fast read  
010 = XIP: Dual I/O fast read  
011 = XIP: Quad output fast read  
100 = XIP: Quad I/O fast read  
101 = Reserved  
110 = Reserved  
111 = Disabled (Default)  
8:6 Output driver  
strength  
000 = Reserved  
001 = 90 Ohms  
010 = Reserved  
011 = 45 Ohms  
100 = Reserved  
101 = 20 Ohms  
110 = Reserved  
111 = 30 Ohms (Default)  
Optimizes the impedance at VCC/2 output volt-  
age.  
5
4
3
2
1
Double transfer  
rate protocol  
0 = Enabled  
1 = Disabled (Default)  
Set DTR protocol as current one. Once enabled,  
all commands will work in DTR.  
Reset/hold  
0 = Disabled  
1 = Enabled (Default)  
Enables or disables HOLD# or RESET# on DQ3.  
Quad I/O  
protocol  
0 = Enabled  
1 = Disabled (Default)  
Enables or disables quad I/O command input  
(4-4-4 mode).  
2
2
Dual I/O  
protocol  
0 = Enabled  
1 = Disabled (Default)  
Enables or disables dual I/O command input  
(2-2-2 mode).  
128Mb  
segment select  
0 = Highest 128Mb segment  
1 = Lowest 128Mb segment (De-  
fault)  
Selects the power-on default 128Mb segment for  
3-byte address operations. See also the extended  
address register.  
CCMTD-1725822587-3368  
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
© 2014 Micron Technology, Inc. All rights reserved.  
28  
 
 
 复制成功!