256Mb, 3V Multiple I/O Serial Flash Memory
Volatile Configuration Register
Table 11: Clock Frequencies – DTR (in MHz)
Notes apply to entire table
Number of
Dummy
Clock Cycles
DUAL OUTPUT
FAST READ
DUAL I/O FAST
READ
QUAD OUTPUT
FAST READ
QUAD I/O FAST
READ
FAST READ
1
59
73
82
90
90
90
90
90
90
90
45
59
68
76
83
90
90
90
90
90
40
49
59
65
75
83
90
90
90
90
26
40
59
65
75
83
90
90
90
90
20
30
39
49
58
68
78
85
90
90
2
3
4
5
6
7
8
9
10 : 14
1. Values are guaranteed by characterization and not 100% tested in production.
Notes:
2. A tuning data pattern (TDP) capability provides applications with data patterns for ad-
justing the data latching point at the host end when the clock frequency is set higher
than 133 MHz in STR mode and higher than 66 MHz in double transfer rate (DTR) mode.
For additional details, refer to TN-25-07: Tuning Data Pattern for MT25Q and MT25T De-
vices.
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
32
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