256Mb, 3V Multiple I/O Serial Flash Memory
Volatile Configuration Register
Supported Clock Frequencies
Table 10: Clock Frequencies – STR (in MHz)
Notes apply to entire table
Number of
Dummy
Clock Cycles
DUAL OUTPUT
FAST READ
DUAL I/O FAST
READ
QUAD OUTPUT
FAST READ
QUAD I/O FAST
READ
FAST READ
94
1
79
60
77
44
61
39
48
2
112
97
3
129
106
86
78
58
4
133
115
97
97
69
5
133
125
106
115
125
133
133
133
133
106
115
125
133
133
133
133
78
6
133
133
86
7
133
133
97
8
9
133
133
106
115
125
133
133
133
10
133
133
11 : 14
133
133
1. Values are guaranteed by characterization and not 100% tested in production.
Notes:
2. A tuning data pattern (TDP) capability provides applications with data patterns for ad-
justing the data latching point at the host end when the clock frequency is set higher
than 133 MHz in STR mode and higher than 66 MHz in double transfer rate (DTR) mode.
For additional details, refer to TN-25-07: Tuning Data Pattern for MT25Q and MT25T De-
vices.
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
31
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