256Mb, 3V Multiple I/O Serial Flash Memory
Flag Status Register
Flag Status Register
Flag status register bits are read by using READ FLAG STATUS REGISTER command. All
bits are volatile and are reset to zero on power-up.
Status bits are set and reset automatically by the internal controller. Error bits must be
cleared through the CLEAR STATUS REGISTER command.
Table 5: Flag Status Register
Bit
Name
Settings
Description
7
Program or
erase
controller
0 = Busy
1 = Ready
Status bit: Indicates whether one of the following
command cycles is in progress: WRITE STATUS
REGISTER, WRITE NONVOLATILE CONFIGURATION
REGISTER, PROGRAM, or ERASE.
6
5
4
Erase suspend
Erase
0 = Clear
1 = Suspend
Status bit: Indicates whether an ERASE operation has been
or is going to be suspended.
0 = Clear
1 = Failure or protection error
Error bit: Indicates whether an ERASE operation has suc-
ceeded or failed.
Program
0 = Clear
1 = Failure or protection error
Error bit: Indicates whether a PROGRAM operation has suc-
ceeded or failed. It indicates, also, whether a CRC check has
succeeded or failed.
3
2
Reserved
0
Reserved
Program sus-
pend
0 = Clear
1 = Suspend
Status bit: Indicates whether a PROGRAM operation has
been or is going to be suspended.
1
Protection
0 = Clear
1 = Failure or protection error
Error bit: Indicates whether an ERASE or PROGRAM opera-
tion has attempted to modify the protected array sector, or
whether a PROGRAM operation has attempted to access the
locked OTP space.
0
Addressing
0 = 3-byte addressing
1 = 4-byte addressing
Status bit: Indicates whether 3-byte or 4-byte address
mode is enabled.
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
25
© 2014 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
