256Mb, 3V Multiple I/O Serial Flash Memory
Nonvolatile Configuration Register
Table 7: Nonvolatile Configuration Register (Continued)
Bit Name
Settings
Description
Notes
0
Number of
address bytes
0 = Enable 4-byte address mode
1 = Enable 3-byte address mode
Defines the number of address bytes for a com-
mand.
during command (Default)
entry
1. The number of cycles must be set to accord with the clock frequency, which varies by the
type of FAST READ command (See Supported Clock Frequencies table). Insufficient dum-
my clock cycles for the operating frequency causes the memory to read incorrect data.
Notes:
2. When bits 2 and 3 are both set to 0, the device operates in quad I/O protocol.
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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