欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT250QL02GABB1E120SATES 参数 Datasheet PDF下载

MT250QL02GABB1E120SATES图片预览
型号: MT250QL02GABB1E120SATES
PDF下载: 下载PDF文件 查看货源
内容描述: [3V, Multiple I/O, 4KB, 32KB, 64KB, Sector Erase]
分类和应用:
文件页数/大小: 97 页 / 1038 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT250QL02GABB1E120SATES的Datasheet PDF文件第29页浏览型号MT250QL02GABB1E120SATES的Datasheet PDF文件第30页浏览型号MT250QL02GABB1E120SATES的Datasheet PDF文件第31页浏览型号MT250QL02GABB1E120SATES的Datasheet PDF文件第32页浏览型号MT250QL02GABB1E120SATES的Datasheet PDF文件第34页浏览型号MT250QL02GABB1E120SATES的Datasheet PDF文件第35页浏览型号MT250QL02GABB1E120SATES的Datasheet PDF文件第36页浏览型号MT250QL02GABB1E120SATES的Datasheet PDF文件第37页  
256Mb, 3V Multiple I/O Serial Flash Memory  
Enhanced Volatile Configuration Register  
Enhanced Volatile Configuration Register  
This register is read from and written to using the READ ENHANCED VOLATILE CON-  
FIGURATION REGISTER and the WRITE ENHANCED VOLATILE CONFIGURATION  
REGISTER commands, respectively. A register download is executed after these com-  
mands, overwriting the internal configuration register settings that determine device  
memory behavior.  
Table 12: Enhanced Volatile Configuration Register  
Bit  
Name  
Settings  
Description  
Notes  
7
Quad I/O protocol  
0 = Enabled  
Enables or disables quad I/O command input  
1
1 = Disabled (Default) (4-4-4 mode).  
6
5
Dual I/O protocol  
0 = Enabled  
1 = Disabled (Default) (2-2-2 mode).  
Enables or disables dual I/O command input  
1
Double transfer rate  
protocol  
0 = Enabled  
Set DTR protocol as current one. Once enabled,  
1 = Disabled (Default, all commands will work in DTR.  
single transfer rate)  
4
Reset/hold  
0 = Disabled  
Enables or disables HOLD# or RESET# on DQ3.  
1 = Enabled (Default)  
(Available only on specified part numbers.)  
3
Reserved  
1
2:0  
Output driver strength 000 = Reserved  
001 = 90 ohms  
Optimizes the impedance at VCC/2 output volt-  
age.  
010 = Reserved  
011 = 45 ohms  
100 = Reserved  
101 = 20 ohms  
110 = Reserved  
111 = 30 ohms (De-  
fault)  
1. When bits 6 and 7 are both set to 0, the device operates in quad I/O protocol. When ei-  
ther bit 6 or 7 is set to 0, the device operates in dual I/O or quad I/O respectively. When a  
bit is set, the device enters the selected protocol immediately after the WRITE EN-  
HANCED VOLATILE CONFIGURATION REGISTER command. The device returns to the de-  
fault protocol after the next power-on or reset. Also, the rescue sequence or another  
WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command will return the de-  
vice to the default protocol.  
Note:  
CCMTD-1725822587-3368  
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
33  
© 2014 Micron Technology, Inc. All rights reserved.  
 
 
 
 复制成功!