256Mb, 3V Multiple I/O Serial Flash Memory
READ MEMORY Operations
READ MEMORY Operations
To initiate a command, S# is driven LOW and the command code is input on DQn, fol-
lowed by input of the address bytes on DQn. The operation is terminated by driving S#
HIGH at any time during data output.
Table 22: READ MEMORY Operations
Operation Name
Description/Conditions
READ (03h)
The device supports 3-byte addressing (default), with A[23:0] input during
address cycle. After any READ command is executed, the device will out-
put data from the selected address. After the boundary is reached, the
device will start reading again from the beginning.
FAST READ (0Bh)
DUAL OUTPUT FAST READ (3Bh)
DUAL INPUT/OUTPUT FAST READ (BBh)
QUAD OUTPUT FAST READ (6Bh)
QUAD INPUT/OUTPUT FAST READ (EBh)
DTR FAST READ (0Dh)
Each address bit is latched in during the rising edge of the clock. The ad-
dressed byte can be at any location, and the address automatically incre-
ments to the next address after each byte of data is shifted out; there-
fore, a die can be read with a single command.
FAST READ can operate at a higher frequency (fC).
DTR DUAL OUTPUT FAST READ (3Dh)
DTR DUAL INPUT/OUTPUT FAST READ (BDh)
DTR QUAD OUTPUT FAST READ (6Dh)
DTR QUAD INPUT/OUTPUT FAST READ (EDh)
QUAD INPUT/OUTPUT WORD READ (E7h)
DTR commands function in DTR protocol regardless of settings in the
nonvolatile configuration register or enhanced volatile configuration reg-
ister; other commands function in DTR protocol only after DTR protocol is
enabled by the register settings.
E7h is similar to the QUAD I/O FAST READ command except that the low-
est address bit (A0) must equal 0 and only four dummy clocks are re-
quired prior to the data output. This command is supported in extended-
SPI and quad-SPI protocols, but not in the DTR protocol; it is ignored it in
dual-SPI protocol.
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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