256Mb, 3V Multiple I/O Serial Flash Memory
Software RESET Operations
Software RESET Operations
RESET ENABLE and RESET MEMORY Commands
To initiate these commands, S# is driven LOW and the command code is input on DQn.
A minimum de-selection time of tSHSL2 must come between RESET ENABLE and RE-
SET MEMORY or reset is not guaranteed. Then, S# must be driven HIGH for the device
to enter power-on reset. A time of tSHSL3 is required before the device can be re-selec-
ted by driving S# LOW.
Table 20: RESET ENABLE and RESET MEMORY Operations
Operation Name
RESET ENABLE (66h)
RESET MEMORY (99h)
Description/Conditions
To reset the device, the RESET ENABLE command must be followed by the RESET MEMORY
command. When the two commands are executed, the device enters a power-on reset con-
dition. It is recommended to exit XIP mode before executing these two commands.
All volatile lock bits, the volatile configuration register, the enhanced volatile configura-
tion register, and the extended address register are reset to the power-on reset default
condition according to nonvolatile configuration register settings.
If a reset is initiated while a WRITE, PROGRAM, or ERASE operation is in progress or sus-
pended, the operation is aborted and data may be corrupted.
Reset is effective after the flag status register bit 7 outputs 1 with at least one byte output.
A RESET ENABLE command is not accepted during WRITE STATUS REGISTER and WRITE
NONVOLATILE CONFIGURATION REGISTER operations.
Figure 16: RESET ENABLE and RESET MEMORY Command
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
C
S#
Reset enable
Reset memory
DQ0
1. Above timing diagram is showed for Extended-SPI Protocol case, however these com-
mands are available in all protocols. In DIO-SPI protocol, the instruction bits are trans-
mitted on both DQ0 and DQ1 pins. In QIO-SPI protocol the instruction bits are transmit-
ted on all four data pins. In Extended-DTR-SPI protocol, the instruction bits are transmit-
ted on DQ0 pin in double transfer rate mode. In DIO-DTR-SPI protocol, the instruction
bits are transmitted on both DQ0 and DQ1 pins in double transfer rate mode. In QIO-
DTR-SPI protocol, the instruction bits are transmitted on all four data pins in double
transfer rate mode.
Note:
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
45
© 2014 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
