256Mb, 3V Multiple I/O Serial Flash Memory
Command Definitions
1. Micron extended SPI protocol is the standard SPI protocol with additional commands
that extend functionality and enable address or data transmission on multiple DQn
lines.
Notes:
2. The command code is always transmitted on DQn = 1, 2, or 4 lines according to the
standard, dual, or quad protocol respectively. However, a command may be able to
transmit address and data on multiple DQn lines regardless of protocol. The protocol
columns show the number of DQn lines a command uses to transmit command, address,
and data information as shown in these examples: command-address-data = 1-1-1, or
1-2-2, or 2-4-4, and so on.
3. The READ SERIAL FLASH DISCOVERY PARAMETER operation accepts only 3-byte address
even if the device is configured to 4-byte address mode.
4. Requires 4 bytes of address if the device is configured to 4-byte address mode.
5. The number of dummy clock cycles required when shipped from Micron factories. The
user can modify the dummy clock cycle number via the nonvolatile configuration regis-
ter and the volatile configuration register.
6. The number of dummy cycles for the READ GENERAL PURPOSE READ REGISTER com-
mand is fixed (8 dummy cycles) and is not affected by dummy cycle settings in the non-
volatile configuration register and volatile configuration register.
7. The general purpose read register is 64 bytes. After the first 64 bytes, the device outputs
00h and does not wrap.
8. The WRITE ENABLE command must be issued first before this operation can be execu-
ted.
9. Formerly referred to as the READ LOCK REGISTER operation.
10. Formerly referred to as the WRITE LOCK REGISTER operation.
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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