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MT250QL01GCBA1ESE0SATES 参数 Datasheet PDF下载

MT250QL01GCBA1ESE0SATES图片预览
型号: MT250QL01GCBA1ESE0SATES
PDF下载: 下载PDF文件 查看货源
内容描述: [3V, Multiple I/O, 4KB, 32KB, 64KB, Sector Erase]
分类和应用:
文件页数/大小: 97 页 / 1038 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb, 3V Multiple I/O Serial Flash Memory  
Active, Standby, and Deep Power-Down Modes  
Active, Standby, and Deep Power-Down Modes  
When S# is LOW, the device is selected and in active power mode. When S# is HIGH, the  
device is deselected but could remain in active power mode until ongoing internal op-  
erations are completed. Then the device goes into standby power mode and device cur-  
rent consumption drops to ICC1.  
Deep power-down mode enbles users to place the device in the lowest power consump-  
tion mode, ICC2. The ENTER DEEP POWER-DOWN command is used to put the device  
in deep power-down mode, and the RELEASE FROM DEEP POWER-DOWN command  
is used to bring the device out of deep power-down mode. Command details are in the  
Command Set table and the DEEP POWER-DOWN Operations section of this data  
sheet.  
Power Loss and Interface Rescue  
If a power loss occurs during a WRITE NONVOLATILE CONFIGURATION REGISTER  
command, after the next power-on, the device might begin in an undetermined state  
(XIP mode or an unnecessary protocol). If this occurs, a power loss recovery sequence  
must reset the device to a fixed state (extended-SPI protocol without XIP) until the next  
power-up.  
If the controller and memory device get out of synchronization, the controller can fol-  
low an interface rescue sequence to reset the memory device interface to power-up to  
the last reset state (as defined by latest nonvolatile configuration register). This resets  
only the interface, not the entire memory device, and any ongoing operations are not  
interrupted.  
After each sequence, the issue should be resolved definitively by running the WRITE  
NONVOLATILE CONFIGURATION REGISTER command again.  
Note: The two steps in each sequence must be in the correct order, and tSHSL2 must be  
at least 50ns for the duration of each sequence.  
The first step for both the power loss recovery and interface rescue sequences is descri-  
bed under "Recovery." The second step in the power loss recovery sequence is under  
"Power Loss Recovery" and the second step in the interface rescue sequence is under  
"Interface Rescue."  
Recovery  
Step one of both the power loss recovery and interface rescue sequences is DQ0 (PAD  
DATA) and DQ3 (PAD HOLD) equal to 1 for the situations listed here:  
• 7 clock cycles within S# LOW (S# becomes HIGH before 8th clock cycle)  
• + 9 clock cycles within S# LOW (S# becomes HIGH before 10th clock cycle)  
• + 13 clock cycles within S# LOW (S# becomes HIGH before 14th clock cycle)  
• + 17 clock cycles within S# LOW (S# becomes HIGH before 18th clock cycle)  
• + 25 clock cycles within S# LOW (S# becomes HIGH before 26th clock cycle)  
• + 33 clock cycles within S# LOW (S# becomes HIGH before 34th clock cycle)  
CCMTD-1725822587-3368  
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 2014 Micron Technology, Inc. All rights reserved.  
 
 
 
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