256Mb, 3V Multiple I/O Serial Flash Memory
ERASE Operations
ERASE Operations
An ERASE operation changes a bit from 0 to 1. Before any ERASE command is initiated,
the WRITE ENABLE command must be executed to set the write enable latch bit to 1; if
not, the device ignores the command and no error bits are set to indicate operation fail-
ure. S# is driven LOW and held LOW until the eighth bit of the last data byte has been
latched in, after which it must be driven HIGH. The operations are self-timed, and dura-
tion is tSSE, tSE, or tBE according to command.
If S# is not driven HIGH, the command is not executed, flag status register error bits are
not set, and the write enable latch remains set to 1. A command applied to a protected
subsector is not executed. Instead, the write enable latch bit remains set to 1, and flag
status register bits 1 and 5 are set.
When the operation is in progress, the program or erase controller bit of the flag status
register is set to 0. In addition, the write in progress bit is set to 1. When the operation
completes, the write in progress bit is cleared to 0. The write enable latch bit is cleared
to 0, whether the operation is successful or not. If the operation times out, the write en-
able latch bit is reset and the erase error bit is set to 1.
The status register and flag status register can be polled for the operation status. When
the operation completes, these register bits are cleared to 1.
Note: For all ERASE operations, noisy or undesirable signal effects can be reduced and
device data protection enhanced by holding S# LOW until the eighth bit of the last data
byte has been latched in; this ensures that the number of clock pulses is a multiple of
one byte before command execution.
Table 30: ERASE Operations
Operation Name
Description/Conditions
SUBSECTOR ERASE (52h/20h)
SECTOR ERASE (D8h)
Sets the selected subsector or sector bits to FFh. Any address within the subsector is valid
for entry. Each address bit is latched in during the rising edge of the clock. The operation
can be suspended and resumed by the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE
RESUME commands, respectively.
BULK ERASE (C7h/60h)
Sets the device bits to FFh.
The command is not executed if any sector is locked. Instead, the write enable latch bit
remains set to 1, and flag status register bits 1 and 5 are set.
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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