256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
f. The full variation in the ratio of the nom inal
41. Random addressing changing and 50 percent of
data changing at every transfer.
42. Random addressing changing and 100 percent of
data changing at every transfer.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0 Volt.
34. The voltage levels used are derived from a m ini-
mum VDD level and the referenced test load. In
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
43. CKE m ust be active (high) during the entire tim e a
refresh command is executed. That is, from the
tim e the AUTO REFRESH com m and is registered,
CKE must be active at each rising clock edge, until
tREF later.
35. VIH overshoot: VIH (MAX) = VDDQ+1.5V for a
pulse width ≤ 3ns and the pulse width can not be
greater than 1/ 3 of the cycle rate. VIL undershoot:
VIL(MIN) = -1.5V for a pulse width ≤ 3ns and the
pulse width can not be greater than 1/ 3 of the
cycle rate.
44. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
36. VDD and VDDQ m ust track each other.
37. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPST
(MAX) condition. tLZ (MIN) will prevail over
tDQSCK (MIN) + tRPRE (MAX) condition.
45. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
46. Leakage num ber reflects the worst case leakage
possible through the m odule pin, not what each
memory device contributes.
47. This is the DC voltage supplied at the DRAM and
is inclusive of all noise up to 20 MHz. Any noise
above 20MHz at the DRAM generated from any
source other than the DRAM istelf may not exceed
the DC voltage range of +2.6V ±0.1V.
t
38. tRPST end point and RPRE begin point are not
referenced to a specific voltage level but specify
when the device output is no longer driving
(tRPST), or begins driving (tRPRE).
39. During initialization, VDDQ, VTT, and VREF must
be equal to or less than VDD + 0.3V. Alternatively,
VTT may be 1.35V maximum during power up,
even if VDD/ VDDQ are 0V, provided a m inim um of
42Ω of series resistance is used between the VTT
supply and the input pin.
48. When an input signal is HIGH or LOW, it is
defined as a steady state logic HIGH or LOW.
40. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
21
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