256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
Ta b le 16: DDR SDRAM Co m p o n e n t Ele ct rica l Ch a ra ct e rist ics a n d
Re co m m e n d e d AC Op e ra t in g Co n d it io n s
Notes: 1–5, 8, 12–15, 29, 31; notes appear on pages 19–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
AC CHARACTERISTICS
-40B
PARAMETER
SYMBOL
MIN
-0.7
0.45
0.45
5
MAX
+0.7
0.55
0.55
7.5
UNITS
NOTES
tAC
tCH
tCL
ns
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
tCK
tCK
ns
26
26
tCK (3)
tCK (2.5)
tCK (2)
tDH
40, 45
40, 45
40, 45
23, 27
23, 27
27
Clock cycle time
CL = 3
CL = 2.5
CL = 2
6
13
ns
ns
ns
ns
ns
ns
7.5
13
0.4
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
tDS
0.4
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
1.75
-0.6
0.35
0.35
+0.6
tCK
tCK
ns
DQS input low pulse width
0.40
1.28
22, 23
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
tCK
tCK
tCK
ns
0.72
0.2
tDSH
tHP
0.2
tCH,tCL
30
tHZ
tLZ
tIHF
+0.70
ns
ns
ns
16, 37
16, 37
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (1 V/ns)
-0.70
0.6
tISF
0.6
0.6
0.6
ns
ns
ns
Address and control input setup time (1 V/ns)
Address and control input hold time (0.5 V/ns)
Address and control input setup time (0.5 V/ns)
tIHS
12
12
tISS
tIPW
tMRD
tQH
tQHS
tRAS
tRAP
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
2.2
2
ns
ns
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
tHP -tQHS
ns
ns
ns
ns
ns
ns
ns
ns
22, 23
30
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
0.50
40
15
55
70
15
15
0.9
0.4
70,000
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
43
tCK
tCK
1.1
0.6
38
38
DQS read preamble
DQS read postamble
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
17
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