256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
controller greater than eight refresh cycles is not
allowed.
31. READs and WRITEs with auto precharge are not
allowed to be issued until tRAS(MIN) can be satis-
fied prior to the internal precharge com m and
being issued.
22. The valid data window is derived by achieving
t
other specifications: tHP (tCK/ 2), tDQSQ, and QH
(tQH = tHP - tQHS). The data valid window derates
in direct porportion to the clock duty cycle and a
practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation
of 45/ 55. Functionality is uncertain when operat-
ing beyond a 45/ 55 ratio.
32. Any positive glitch must be less than 1/ 3 of the
clock and not more than +400mV or 2.9V, which-
ever is less. Any negative glitch must be less than 1/
3 of the clock cycle and not exceed either -300mV
or 2.4V, whichever is more positive. However, the
DC average cannot be below 2.5V minimum.
33. Normal Output Drive Curves:
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (tRFC [MIN]) else
CKE is LOW (i.e., during standby).
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 7,
Pull-Down Characteristics, on page 20.
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 7, Pull-Down Characteristics,
on page 20.
c. The full variation in driver pull-up current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Up Characteristics, on page 20.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 8, Pull-Up Characteristics, on page 20.
e. The full variation in the ratio of the maximum
to m inim um pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the sam e voltage and tem perature.
25. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level, VIL (AC)
or VIH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
maintain at least the target DC level, VIL (DC)
or VIH (DC).
26. CK and CK# input slew rate must be ≥ 1V/ ns (2V/
ns differentially).
27. DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. DQ/ DM/ DQS
slew rates less than 0.5V/ ns are not allowed. If slew
rate exceeds 4V/ ns, functionality is uncertain.
28. VDD m ust not vary m ore than 4 percent if CKE is
not active while any bank is active.
29. The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
t
t
30. tHP min is the lesser of CL minimum and CH
minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.
Fig u re 7: Pu ll-Do w n Ch a ra ct e rist ics
Fig u re 8: Pu ll-Up Ch a ra ct e rist ics
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
20
MICRON [ MICRON TECHNOLOGY ]
