256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
Ta b le 14: IDD Sp e cifica t io n s a n d Co n d it io n s – 1GB
DDR SDRAM components only
Notes: 1–5, 8, 10, 12; notes appear on pages 19–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
MAX
PARAMETER/CONDITION
SYM
-40B
UNITS
NOTES
IDD0a
1,440
mA
21, 41
OPERATING CURRENT: One device bank; Active-Precharge;
t
t
tRC = RC (MIN); tCK = CK (MIN); DQ, DM and DQS inputs
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
IDD1a
1,710
mA
21, 41
OPERATING CURRENT: One device bank; Active -Read Precharge;
t
t
Burst = 4; tRC = RC (MIN); tCK = CK (MIN); IOUT = 0mA; Address
and control inputs changing once per clock cycle
IDD2Pb
IDD2Fb
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
90
mA
mA
21, 28,
43
t
idle; Power-down mode; tCK = CK (MIN); CKE = (LOW)
990
44
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
tCK = CK MIN; CKE = HIGH; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ, DQS, and DM
IDD3Pb
IDD3Nb
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode; CK = CK (MIN); CKE = LOW
810
mA
mA
21, 28,
43
t
t
1,080
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
t
t
bank; Active-Precharge; tRC = RAS (MAX); tCK = CK (MIN); DQ,
DM andDQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
IDD4Ra
1,755
1,800
mA
mA
21, 41
21
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
t
cycle; tCK = CK (MIN); IOUT = 0mA
IDD4Wa
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
t
clock cycle; tCK = CK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
tREFC = tRFC (MIN)
tREFC = 7.8125µs
Standard
6,210
198
mA
mA
mA
mA
43
24, 43
9
IDD5b
IDD5Ab
IDD6b
AUTO REFRESH CURRENT
90
SELF REFRESH CURRENT: CKE ≤ 0.2V
IDD7a
4,095
20, 42
OPERATING CURRENT: Four device bank interleaving READs
t
t
(BL = 4) with auto precharge, tRC = RC (MIN); tCK = CK (MIN);
Address and control inputs change only during Active READ, or
WRITE commands
NOTE:
a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD
2P (CKE LOW) mode.
b: Value calculated reflects all module ranks in this operating condition.
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
15
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