OBSOLETE
4, 8 MEG x 36
PARITY DRAM SIMMs
READ CYCLE
tRC
tRAS
V IH
V IL
tCSH
tRSH
tCAS
tRRH
tRP
RAS#
CAS#
ADDR
WE#
DQ
,,, , ,,,,
,,, , , , , ,, ,
,, ,
,
, ,
,,
,,
,
tCRP
tRCD
V IH
V IL
tAR
tRAD
tRAH
tASR
tASC
tCAH
V IH
V IL
ROW
COLUMN
ROW
tRCS
tRCH
V IH
V IL
tAA
tRAC
tCAC
tCLZ
tOFF
V IOH
V IOL
OPEN
VALID DATA
OPEN
TIMING PARAMETERS
-6
SYMBOL
t
AA
t
AR
t
ASC
t
ASR
t
CAC
t
CAH
t
CAS
t
CLZ
t
CRP
t
CSH
t
OFF
,
-6
DON’T CARE
UNDEFINED
MIN
45
0
0
MAX
30
15
10
15
3
10
60
3
15
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t
RAC
t
RAD
t
RAH
t
RAS
t
RC
t
RCD
t
RCH
t
RCS
t
RP
t
RRH
t
RSH
MIN
15
10
60
110
20
0
0
40
0
15
MAX
60
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
„1997,
Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
