OBSOLETE
4, 8 MEG x 36
PARITY DRAM SIMMs
EARLY WRITE CYCLE
t
RC
t
t
RAS
RP
V
IH
RAS#
CAS#
ADDR
V
IL
t
CSH
t
RSH
t
t
t
t
CRP
RCD
CAS
V
V
IH
IL
t
AR
t
t
RAD
RAH
t
t
ASC
ASR
CAH
V
V
IH
IL
ROW
COLUMN
ROW
t
CWL
t
t
t
t
RWL
WCR
WCH
WP
t
WCS
V
V
IH
IL
WE#
DQ
t
t
DS
DH
V
IOH
IOL
VALID DATA
V
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
-6
SYMBOL
MIN
45
0
MAX
UNITS
ns
SYMBOL
MIN
10
60
110
20
40
15
15
10
45
0
MAX
UNITS
ns
t
t
AR
RAH
t
t
ASC
ns
RAS
10,000
ns
t
t
ASR
0
ns
RC
ns
t
t
CAH
10
15
10
60
15
10
0
ns
RCD
ns
t
t
CAS
10,000
ns
RP
ns
t
t
CRP
ns
RSH
ns
t
t
CSH
ns
RWL
ns
t
t
CWL
ns
WCH
ns
t
t
DH
ns
WCR
ns
t
t
DS
ns
WCS
ns
t
t
RAD
15
ns
WP
10
ns
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
10