OBSOLETE
4, 8 MEG x 36
PARITY DRAM SIMMs
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t
t
RP
RASP
V
IH
RAS#
CAS#
ADDR
V
IL
t
RSH
t
t
CSH
PC
t
t
t
t
t
t
CP
CRP
RCD
CAS
CP
CAS
V
V
IH
IL
t
AR
t
RAD
RAH
t
t
CAH
t
t
t
t
CAH
ASC
ASR
ASC
V
V
IH
IL
ROW
COLUMN
COLUMN
t
ROW
CWL
t
t
t
t
RCS
RWL
WP
t
WCS
WCH
V
V
IH
IL
WE#
DQ
t
CAC
NOTE 1
t
t
t
t
DH
CLZ
OFF
DS
V
VALID
DATA
OH
OL
VALID DATA
OPEN
V
t
AA
t
RAC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
-6
SYMBOL
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
MIN
3
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AA
30
OFF
15
t
t
AR
45
0
PC
35
t
t
ASC
RAC
60
t
t
ASR
0
RAD
15
10
60
20
0
t
t
CAC
15
RAH
t
t
CAH
10
15
3
RASP
125,000
t
t
CAS
10,000
RCD
t
t
CLZ
RCS
t
t
CP
10
10
60
15
10
0
RP
40
15
15
10
0
t
t
CRP
RSH
t
t
CSH
RWL
t
t
CWL
WCH
t
t
DH
WCS
t
t
DS
WP
10
NOTE: 1. Do not drive data prior to tristate.
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
13
MICRON [ MICRON TECHNOLOGY ]
