OBSOLETE
4, 8 MEG x 36
PARITY DRAM SIMMs
HIDDEN REFRESH CYCLE 20
(WE# = HIGH)
t
t
t
RAS
RAS
RP
V
IH
RAS#
CAS#
V
IL
t
t
t
t
CHR
CRP
RCD
RSH
V
V
IH
IL
t
t
AR
RAD
t
t
t
t
CAH
ASR
RAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
t
AA
t
t
t
RAC
CAC
CLZ
t
OFF
V
V
IOH
IOL
DQ
OPEN
VALID DATA
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
-6
SYMBOL
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
15
UNITS
ns
t
t
t
t
t
t
t
t
t
AA
30
OFF
RAC
RAD
RAH
RAS
RCD
RP
3
t
AR
45
0
ns
60
ns
t
ASC
ns
15
10
60
20
40
15
ns
t
ASR
0
ns
ns
t
CAC
15
ns
10,000
ns
t
CAH
10
15
3
ns
ns
t
CHR
ns
ns
t
CLZ
ns
RSH
ns
t
CRP
10
ns
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
15
MICRON [ MICRON TECHNOLOGY ]
