欢迎访问ic37.com |
会员登录 免费注册
发布采购

M58BW016FB 参数 Datasheet PDF下载

M58BW016FB图片预览
型号: M58BW016FB
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 512千位×32 ,引导块,爆) [16 Mbit (512 Kbit x 32, boot block, burst)]
分类和应用:
文件页数/大小: 70 页 / 1283 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号M58BW016FB的Datasheet PDF文件第18页浏览型号M58BW016FB的Datasheet PDF文件第19页浏览型号M58BW016FB的Datasheet PDF文件第20页浏览型号M58BW016FB的Datasheet PDF文件第21页浏览型号M58BW016FB的Datasheet PDF文件第23页浏览型号M58BW016FB的Datasheet PDF文件第24页浏览型号M58BW016FB的Datasheet PDF文件第25页浏览型号M58BW016FB的Datasheet PDF文件第26页  
Bus operations  
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB  
Valid Data Ready may be configured (by bit M8 of burst configuration register) to be valid  
immediately at the valid clock edge or one data cycle before the valid clock edge.  
Synchronous burst read will be suspended if Burst Address Advance, B, goes High, VIH.  
If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid.  
If Output Enable, G, is at VIH or Output Disable, GD, is at VIL, but the Burst Address  
Advance, B, is at VIL the internal Burst Address counter is incremented at each Burst Clock  
K valid edge.  
The synchronous burst read timing diagrams and AC characteristics are described in the  
AC and DC parameters section. See Figure 13, Figure 14, Figure 15 and Figure 16, and  
Table 20.  
3.2.2  
Synchronous burst read suspend  
During a synchronous burst read operation it is possible to suspend the operation, freeing  
the data bus for other higher priority devices.  
A valid synchronous burst read operation is suspended when both Output Enable and Burst  
Address Advance are High, VIH. The Burst Address Advance going High, VIH, stops the  
burst counter and the Output Enable going High, VIH, inhibits the data outputs. The  
synchronous burst read operation can be resumed by setting Output Enable Low.  
Table 6.  
Synchronous burst read bus operations(1)(2)  
A0-A18  
DQ0-DQ31  
(3)  
Bus operation  
Step  
E
G
GD RP  
K
L
B
Address Latch  
Read  
V
V
X
V
V
V
V
T
V
X
Address input  
Data output  
High-Z  
IL  
IL  
IL  
IL  
IH  
IH  
IH  
IH  
IH  
IL  
IH  
IH  
IH  
V
V
V
V
V
T
X
T
V
V
V
V
IL  
IH  
IL  
Read Suspend  
Read Resume  
V
X
V
IH  
IH  
Synchronous  
burst read  
V
V
V
V
Data output  
IL  
IH  
IL  
IL  
Burst Address  
Advance  
V
V
X
V
V
T
V
High-Z  
IL  
IH  
IH  
IH  
IH  
Read Abort, E  
V
X
X
X
X
X
X
X
High-Z  
High-Z  
IH  
Read Abort, RP  
X
X
V
X
X
IL  
1. X = don't care, V or V  
.
IH  
IL  
2. M15 = 0, bit M15 is in the burst configuration register.  
3. T = transition, see M6 in the burst configuration register for details on the active edge of K.  
22/70