M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
Bus operations
3.1.3
Asynchronous page read
Asynchronous page read operations are used to read from several addresses within the
same memory page. Each memory page is 4 double-words and is addressed by the
address inputs A0 and A1.
Data is read internally and stored in the page buffer. Valid bus operations are the same as
asynchronous bus read operations but with different timings. The first read operation within
the page has identical timings, subsequent reads within the same page have much shorter
access times. If the page changes then the normal, longer timings apply again. Page read
does not support latched controlled read.
See Figure 10: Asynchronous page read AC waveforms, and Table 18: Asynchronous page
read AC characteristics, for details on when the outputs become valid.
3.1.4
Asynchronous bus write
Asynchronous bus write operations write to the command interface to send commands to
the memory or to latch addresses and input data to program. Bus write operations are
asynchronous, the clock, K, is don’t care during bus write operations.
A valid asynchronous bus write operation begins by setting the desired address on the
address inputs, and setting Chip Enable, Write Enable and Latch Enable Low, VIL, and
Output Enable High, VIH, or Output Disable Low, VIL. The address inputs are latched by the
command interface on the rising edge of Chip Enable or Write Enable, whichever occurs
first. Commands and input data are latched on the rising edge of Chip Enable, E, or Write
Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable
Low, during the whole asynchronous bus write operation.
See Figure 11: Asynchronous write AC waveforms, and Table 19: Asynchronous write and
latch controlled write AC characteristics, for details of the timing requirements.
3.1.5
Asynchronous latch controlled bus write
Asynchronous latch controlled bus write operations write to the command interface to send
commands to the memory or to latch addresses and input data to program. Bus write
operations are asynchronous, the clock, K, is don’t care during bus write operations.
A valid asynchronous latch controlled bus write operation begins by setting the desired
address on the address inputs and pulsing Latch Enable Low, VIL. The address inputs are
latched by the command interface on the rising edge of Latch Enable, Write Enable or Chip
Enable, whichever occurs first. Commands and input data are latched on the rising edge of
Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain
High, and Output Disable Low, during the whole asynchronous bus write operation.
See Figure 12: Asynchronous latch controlled write AC waveforms, and Table 19:
Asynchronous write and latch controlled write AC characteristics, for details of the timing
requirements.
3.1.6
Output Disable
The data outputs are high impedance when the Output Enable, G, is at VIH or Output
Disable, GD, is at VIL.
19/70
MICRON [ MICRON TECHNOLOGY ]
