M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
Bus operations
Table 7.
Bit
Burst configuration register
Description
Value
Description
Synchronous burst read
0
1
M15
M14
Read select
Asynchronous read (default at power-on)
Reserved (default value)
Reserved (default value)
Reserved
0
000
001
010
011
100
101
110
111
0
(2)
4, 4-1-1-1
(3)
5
6
7
8
, 5-1-1-1, 5-2-2-2
, 6-1-1-1, 6-2-2-2
, 7-1-1-1, 7-2-2-2
, 8-1-1-1, 8-2-2-2
(1)
M13-M11
X-Latency
(3)
(3)
(3)
Reserved
M10
M9
Reserved (default value)
One burst clock cycle (default value)
Two burst clock cycles
0
(4)
Y-Latency
1
R valid Low during valid burst clock edge (default
value)
0
M8
Valid data ready
1
0
R valid Low 1 data cycle before valid burst clock edge
Interleaved (default value)
Sequential
M7
M6
Burst type
1
0
Falling burst clock edge (default value)
Rising burst clock edge
Reserved (default value)
Reserved
Valid clock edge
1
00
01
10
11
M5-M4
M3
Reserved
Reserved
0
Wrap (default value)
No wrap
Wrapping
1
000
001
010
011
100
101
110
111
Reserved (default value)
4 double-words
8 double-words
Reserved
M2-M0
Burst length
Reserved
Reserved
Reserved
Continuous
1. X latencies can be calculated as: (t
– t
+ t
) + t
< (X -1) t . (X is an integer
AVQV
LLKH
QVKH
SYSTEM MARGIN K
number from 4 to 8, t is the clock period and t
K
is the time margin required for the
SYSTEM MARGIN
calculation).
2. This feature is available for the M58BW016F version up to the full operative frequency of 56 MHz, and for
the M58BW016D version only if the operative frequency is below 45 MHz.
3. The M58BW016F version has a maximum operative frequency of 66 MHz, fully factory tested.
4. Y latencies can be calculated as: t
+ t
+ t
< Y t
KHQV
SYSTEM MARGIN
QVKH K.
25/70
MICRON [ MICRON TECHNOLOGY ]
