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M58BW016FB 参数 Datasheet PDF下载

M58BW016FB图片预览
型号: M58BW016FB
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 512千位×32 ,引导块,爆) [16 Mbit (512 Kbit x 32, boot block, burst)]
分类和应用:
文件页数/大小: 70 页 / 1283 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Bus operations  
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB  
3.1.7  
Standby mode  
When Chip Enable is High, VIH, and the Program/Erase controller is idle, the memory enters  
Standby mode, the power consumption is reduced to the standby level and the Data  
inputs/outputs pins are placed in the high impedance state regardless of Output Enable,  
Write Enable or Output Disable inputs.  
3.1.8  
Automatic low power mode  
If there is no change in the state of the bus for a short period of time during asynchronous  
bus read operations the memory enters auto low power mode where the internal supply  
current is reduced to the auto-standby supply current. The data inputs/outputs will still  
output data if a bus read operation is in progress.  
Automatic low power is only available in asynchronous read modes.  
3.1.9  
Power-down mode  
The memory is in power-down when Reset/Power-down, RP, is at VIL. The power  
consumption is reduced to the power-down level and the outputs are high impedance,  
independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable,  
W, inputs.  
3.1.10  
Electronic signature  
Two codes identifying the manufacturer and the device can be read from the memory  
allowing programming equipment or applications to automatically match their interface to  
the characteristics of the memory. The electronic signature is output by giving the Read  
Electronic Signature command. The manufacturer code is output when all the address  
inputs are at VIL. The device code is output when A1 is at VIH and all the other address pins  
are at VIL (see Table 5: Asynchronous read electronic signature operation). Issue a Read  
Memory Array command to return to read mode.  
Table 4.  
Bus operation  
Asynchronous bus operations(1)  
Step  
E
G
GD  
W
RP  
L
A0-A18 DQ0-DQ31  
Asynchronous bus read  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Address Data output  
IL  
IL  
IL  
IL  
IL  
IL  
IL  
IL  
IL  
IH  
IL  
IH  
IH  
IH  
IH  
IH  
IH  
IH  
IH  
IH  
IH  
IH  
IH  
IH  
IH  
IH  
IL  
IL  
Address Latch  
Read  
V
V
V
V
V
V
V
V
V
V
V
Address  
X
High-Z  
IH  
IL  
IH  
IH  
Asynchronous latch  
controlled bus read  
V
V
V
V
V
Data output  
IL  
IL  
IH  
IH  
Asynchronous page read  
Asynchronous bus write  
X
Address Data output  
Address Data input  
V
X
V
V
V
IL  
IL  
IL  
Address Latch  
Write  
V
V
V
Address  
High-Z  
Data input  
High-Z  
IL  
IH  
IH  
IH  
IH  
Asynchronous latch  
controlled bus write  
V
V
X
V
V
X
X
X
X
X
IL  
IH  
IH  
IH  
Output Enable, G  
Output Disable, GD  
Standby  
V
V
V
X
IH  
V
V
X
X
X
High-Z  
IL  
IL  
V
X
X
X
High-Z  
Reset/power-down  
1. X = don’t care.  
X
X
X
X
V
High-Z  
IL  
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