256Mb: 3V Embedded Parallel NOR Flash
Registers
6. When DQ5 is set to 1, a READ/RESET command must be issued before any subsequent
command.
Table 6: Operations and Corresponding Bit Settings
Note 1 applies to entire table
Operation
Address
DQ7
DQ7#
DQ7#
DQ6
DQ5
DQ3
DQ2
No toggle
–
DQ1
RY/BY# Notes
PROGRAM
Any address
Any address
Toggle
Toggle
0
0
–
–
0
–
0
0
2
PROGRAM during
ERASE SUSPEND
ENHANCED
BUFFERED
PROGRAM
Any address
Any address
–
Toggle
Toggle
0
0
–
–
–
–
–
0
0
BUFFERED
DQ7#
1
2
PROGRAM ABORT
PROGRAM error
CHIP ERASE
Any address
Any address
DQ7#
Toggle
Toggle
1
0
0
0
0
0
0
–
1
0
0
1
1
–
–
–
–
–
–
–
–
–
–
–
High-Z
0
0
0
0
0
1
Toggle
0
BLOCK ERASE
before time-out
Erasing block
Toggle
Toggle
0
0
Non-erasing block
Erasing block
Toggle
No toggle
Toggle
BLOCK ERASE
Toggle
0
Non-erasing block
Erasing block
Toggle
No toggle
Toggle
0
ERASE SUSPEND
No toggle
High-Z
High-Z
High-Z
Non-erasing block
Outputs memory array data as if in read mode
BLOCK ERASE
error
Good block
address
0
Toggle
1
1
No toggle
Faulty block
address
0
Toggle
1
1
Toggle
–
High-Z
1. Unspecified data bits should be ignored.
2. DQ7# for buffer program is related to the last address location loaded.
Notes:
PDF: 09005aef84bd3b68
m29w_256mb.pdf - Rev. C 7/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
15
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