256Mb: 3V Embedded Parallel NOR Flash
Bus Operations
Automatic standby enables low power consumption during read mode. When CMOS
levels (VCC ± 0.3 V) drive the bus, and following a READ operation and a period of inac-
tivity specified in DC Characteristics, the memory enters automatic standby as internal
supply current is reduced to ICC2. Data I/O signals still output data if a READ operation
is in progress. Depending on load circuits connected with data bus, VCCQ can have a
null consumption when the memory enters automatic standby.
Output Disable
Reset
Data I/Os are High-Z when OE# is HIGH.
During reset mode, the device is deselected, and outputs are High-Z. The device is in
reset mode when RST# is LOW. Power consumption is reduced to standby level inde-
pendently from CE#, OE#, or WE# inputs.
PDF: 09005aef84bd3b68
m29w_256mb.pdf - Rev. C 7/13 EN
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