128Mb 3V Embedded Parallel NOR Flash
Program Operations
The PROGRAM SUSPEND command may also be issued during a PROGRAM operation
while an erase is suspended. In this case, data may be read from any address not in
erase suspend or program suspend mode. To read from the extended memory block
area (one-time programmable area), the ENTER/EXIT EXTENDED MEMORY BLOCK
command sequences must be issued.
The system may also issue the AUTO SELECT command sequence when the device is in
program suspend mode. The system can read as many auto select codes as required.
When the device exits auto select mode, the device reverts to program suspend mode
and is ready for another valid operation.
The PROGRAM SUSPEND operation is aborted by performing a device reset or power-
down. In this case, data integrity cannot be ensured, and it is recommended that the
words or bytes that were aborted be reprogrammed.
PROGRAM RESUME Command
The PROGRAM RESUME (30h) command must be issued to exit a program suspend
mode and resume a PROGRAM operation. The controller can use DQ7 or DQ6 status
bits to determine the status of the PROGRAM operation. After a PROGRAM RESUME
command is issued, subsequent PROGRAM RESUME commands are ignored. Another
PROGRAM SUSPEND command can be issued after the device has resumed program-
ming.
ENHANCED BUFFERED PROGRAM Command
The ENHANCED BUFFERED PROGRAM command (x16 only) makes use of a 256-word
write buffer to speed up programming. Each write buffer has the same A22-A8 address-
es. This command dramatically reduces system programming time compared to both
the standard non-buffered PROGRAM command and the WRITE TO BUFFER com-
mand.
When issuing the ENHANCED BUFFERED PROGRAM command, the VPP/WP pin can
be held HIGH or raised to VPPH (see Program/Erase Characteristics). The following suc-
cessive steps are required to issue the ENHANCED BUFFERED PROGRAM command:
The ENHANCED BUFFERED PROGRAM command begins with two unlock cycles, fol-
lowed by one bus write cycle that sets up the command. The setup code can be ad-
dressed to any location within the targeted block. Next, another bus write cycle loads
the first address and data to be programmed. There a total of 256 address and data load-
ing cycles. To program the content of the write buffer, the ENHANCED BUFFERED
PROGRAM command must be followed by an ENHANCED BUFFERED PROGRAM
CONFIRM command. The command ends with an internal enhanced buffered program
confirm cycle.
Address/data cycles must be loaded in an increasing address order, from A[7:0] =
00000000 to A[7:0] = 11111111 until all 256 words are loaded. Invalid address combina-
tions or the incorrect sequence of bus WRITE cycles will abort the WRITE TO BUFFER
PROGRAM command.
The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a WRITE TO BUFFER PROGRAM operation.
An external 12V supply can be used to improve programming efficiency.
PDF: 09005aef84daa141
m29w_128mb.pdf - Rev. A 7/13 EN
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