256Mb: 3V Embedded Parallel NOR Flash
Program Operations
most blocks, depending on the part number. The following successive steps are re-
quired to issue the WRITE TO BUFFER PROGRAM command:
First, two UNLOCK cycles are issued. Next, a third bus WRITE cycle sets up the WRITE
TO BUFFER PROGRAM command. The set-up code can be addressed to any location
within the targeted block. Then, a fourth bus WRITE cycle sets up the number of words
to be programmed. Value n is written to the same block address, where n + 1 is the
number of words to be programmed. Value n + 1 must not exceed the size of the pro-
gram buffer, or the operation will abort. A fifth cycle loads the first address and data to
be programmed. Last, n bus WRITE cycles load the address and data for each word into
the program buffer. Addresses must lie within the range from the start address +1 to the
start address + (n - 1).
Optimum programming performance and lower power usage are achieved by aligning
the starting address at the beginning of a 32-word boundary; otherwise, programming
time doubles. All addresses used in the operation must lie within the same page.
To program the content of the program buffer, this command must be followed by a
WRITE TO BUFFER PROGRAM CONFIRM command.
If an address is written several times during a WRITE TO BUFFER PROGRAM operation,
the address/data counter will be decremented at each data load operation, and the data
will be programmed to the last word loaded into the buffer.
Invalid address combinations or the incorrect sequence of bus WRITE cycles will abort
the WRITE TO BUFFER PROGRAM command.
The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a WRITE TO BUFFER PROGRAM operation.
The WRITE TO BUFFER PROGRAM command should not be used to change a bit set to
0 back to 1, and an attempt to do so is masked during the operation. Rather than the
WRITE BUFFER PROGRAM command, the ERASE command should be used to set
memory bits from 0 to 1.
The WRITE TO BUFFER PROGRAM command can be suspended and then resumed by
issuing a PROGRAM SUSPEND command and then a PROGRAM RESUME command,
respectively.
After the WRITE TO BUFFER PROGRAM operation has completed, the memory will re-
turn to read mode, unless an error has occurred. When an error occurs, a read operation
from the bank being programmed will continue to output the status register. A read op-
eration from any bank other than the one being programmed will output the memory
array content.
PDF: 09005aef84ecabef
m29dw_256g.pdf - Rev. A 10/12 EN
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