M25P128
DC and AC parameters
(1)
Table 15. AC characteristics for 65 nm devices (continued)
Test conditions specified in Table 11 and Table 12
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tDSU Data In Setup Time
2
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDH
Data In Hold Time
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
4
4
tCSH S Deselect Time
50
(2)
tSHQZ
tDIS Output Disable Time
8
8
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tV
Clock Low to Output Valid
Output Hold Time
tHO
1
4
4
4
4
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD to Output Low-Z
(3)
tHHQX
tLZ
8
8
(3)
tHLQZ
tHZ
HOLD to Output High-Z
(5)
tWHSL
Write Protect Setup Time
Write Protect Hold Time
20
(5)
tSHWL
100
(3)
tVPPHSL
Enhanced Program Supply Voltage
High to Chip Select Low
200
ns
s
(6)
tW
Write Status Register Cycle Time
1.3
0.5
15
5
Page Program Cycle Time (256 Bytes)
int(n/8) x
0.015(8)
Page Program Cycle Time (n Bytes)
(7)
tPP
ms
Page Program Cycle Time (VPP
VPPH) (256 Bytes)
=
0.4(3)
tSE
tSE
tBE
tBE
Sector Erase Cycle Time
1.6
1.6
3
s
s
s
s
Sector Erase Cycle Time (VPP = VPPH
Bulk Erase Cycle Time
)
3
130
120
250
250
Bulk Erase Cycle Time (VPP = VPPH
)
1. 65 nm process technology devices are identified by the process identification digit ‘A’ in the device marking
and process letter "B" in the part number.
2. tCH and tCL must be greater than or equal to 1/fC (max).
3. Value is guaranteed by characterization, not 100% tested in production.
4. Expressed as a slew-rate.
5. Only applicable as a constraint for WRSR instruction when SRWD is set to 1.
6. VPPH should be kept at a valid level until the program or erase operation has completed and its result
(success or failure) is known.
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MICRON [ MICRON TECHNOLOGY ]
