M25P128
Initial delivery state
Figure 18. Power-up timing
V
CC
V
(max)
CC
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
V
(min)
CC
tVSL
Read Access allowed
Device fully
accessible
Reset State
of the
Device
V
WI
tPUW
time
AI04009C
(1)
Table 8.
Symbol
Power-up timing and V threshold for 65 nm devices
WI
Parameter
Min.
Max.
Unit
(2)
tVSL
VCC(min) to S Low
200
400
1.5
µs
µs
V
(2)
tPUW
Time delay to Write instruction
Write Inhibit Voltage
VWI
2.5
1. 65 nm technology devices are identified by the process identification digit ‘A’ in the device marking and
process letter "B" in the part number.
2. These parameters are characterized only.
Table 9.
Symbol
Power-up timing and V threshold for 130 nm devices
WI
Parameter
Min.
Max.
Unit
(1)
tVSL
VCC(min) to S Low
60
1
µs
ms
V
(2)
tPUW
Time delay to Write instruction
Write Inhibit Voltage
10
VWI
1.5
2.5
1. These parameters are characterized only.
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
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