Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Table 27: STS Configuration Register and Coding Definitions
D7
D6
D5
D4
D3
D2
D1
D0
Pulse on
Program
Pulse on
Erase
Reserved3
Complete1
Complete1
D[1:0] = STS Configuration Codes2
Notes
00 = default, level mode;
device ready indication
Controls HOLD to a memory controller to prevent accessing a flash memory
subsystem while any flash device's WSM is busy.
Generates a system interrupt pulse when any flash device in an array has
completed a block erase. Helpful for reformatting blocks after file system free
space reclamation or “cleanup.”
01 = pulse on Erase Complete
10 = pulse on Program Complete
Not supported on this device.
Generates system interrupts to trigger servicing of flash arrays when either
erase or program operations are completed, when a common interrupt service
routine is desired.
11 = pulse on Erase or Program Complete
Notes:
1.
2.
3.
When configured in one of the pulse modes, STS pulses low with a typical pulse width of 500 ns.
An invalid configuration code will result in both SR.4 and SR.5 being set.
Reserved bits are invalid should be ignored.
9.8
Security and Protection
J3 65 nm SBC device offers both hardware and software security features. Block lock
operations, PRs and VPEN allow users to implement various levels of data protection.
9.8.1
Normal Block Locking
J3 65 nm SBC has the capability of Flexible Block Locking (locked blocks remain locked
upon reset or power cycle): All blocks within the device are in unlocked state when ship
from Numonyx. Blocks can be locked individually by issuing the Set Block Lock Bit
command sequence to any address within a block. Once locked, blocks remain locked
when power is removed, or when the device is reset.
All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits
command sequence to any device address. Locked blocks cannot be erased or
programmed. Table 28 summarizes the command bus-cycles.
Table 28: Block Locking Command Bus-Cycles
Setup Write Cycle
Confirm Write Cycle
Command
Address Bus
Data Bus
Address Bus
Data Bus
Set Block Lock Bit
Clear Block Lock Bits
Block Address
Device Address
0060h
0060h
Block Address
Device Address
0001h
00D0h
After issuing the Set Block Lock Bit setup command or Clear Block Lock Bits setup
command, the device’s read mode is automatically changed to Read Status Register
mode. After issuing the confirm command, completion of the operation is indicated by
STS (in RY/BY# mode) going high and SR.7 = 1.
Blocks cannot be locked or unlocked while programming or erasing, or while the device
is suspended. Reliable block lock and unlock operations occur only when VCC and VPEN
are valid. When VPEN ≤ VPENLK, block lock-bits cannot be changed.
Datasheet
42
Jan 2011
208032-03