Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
When the set lock-bit operation is complete, SR.4 should be checked for any error.
When the clear lock-bit operation is complete, SR.5 should be checked for any error.
Errors bits must be cleared using the Clear Status Register command.
Block lock-bit status can be determined by first issuing the Read Device Information
command, and then reading from <block base address> + 02h. DQ0 indicates the lock
status of the addressed block (0 = unlocked, 1 = locked).
9.8.2
9.8.3
Configurable Block Locking
J3 65 nm SBC devices feature user-configurable block locking. This feature can be
implemented to protect and/or secure the user’s system. The user can individually set
each block as Non-Volatile Temporary, Non-Volatile Semi-Permanent or Non-Volatile
Permanent. For additional information and collateral, please contact the sales
representative.
Password Access
Password Access is a security enhancement offered on the J3 65 nm SBC device. This
feature protects information stored in main-array memory blocks by preventing content
alteration or reads, until a valid 64-bit password is received. Password Access may be
combined with Non-Volatile Protection and/or Volatile Protection to create a multi-
tiered solution.
Please contact your Numonyx Sales for further details concerning Password Access.
9.8.4
128-bit OTP Protection Register
J3 65 nm SBC includes a 128-bit Protection Register (PR) that can be used to increase
the security of a system design. For example, the number contained in the PR can be
used to “match” the flash component with other system components such as the CPU
or ASIC, hence preventing device substitution.
The 128-bits of the PR are divided into two 64-bit segments:
• One segment is programmed at the Numonyx factory with a unique unalterable 64-
bit number.
• The other segment is left blank for customer designers to program as desired. Once
the customer segment is programmed, it can be locked to prevent further
programming.
9.8.5
9.8.6
Reading the 128-bit OTP Protection Register
The Protection Register is read in Identification Read mode. The device is switched to
this mode by issuing the Read Identifier command (0090h). Once in this mode, read
cycles from addresses shown in Table 31, “Word-Wide Protection Register Addressing”
or Table 32, “Byte-Wide Protection Register Addressing” retrieve the specified
information. To return to Read Array mode, write the Read Array command (00FFh).
Programming the 128-bit OTP Protection Register
PR bits are programmed using the two-cycle Program OTP Register command. The 64-
bit number is programmed 16 bits at a time for word-wide configuration and eight bits
at a time for byte-wide configuration. First write the Protection Program Setup
command, 00C0h. The next write to the device will latch in address and data and
program the specified location. The allowable addresses are shown in Table 31, “Word-
Wide Protection Register Addressing” on page 45 or Table 32, “Byte-Wide Protection
Register Addressing” on page 45. See Figure 24, “Protection Register Programming
Jan 2011
208032-03
Datasheet
43
MICRON [ MICRON TECHNOLOGY ]
