Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Flowchart” on page 56. Any attempt to address Program OTP Register command
outside the defined PR address space will result in a Status Register error (SR.4 will be
set). Attempting to program a locked PR segment will result in a Status Register error
(SR.4 and SR.1 will be set).
Table 29: Programming the 128-bit Protection Register Command Bus-Cycles
First Bus Cycle
Second Bus Cycle
Command
Address Bus
Device Address
Data Bus
Address Bus
Register Offset
Data Bus
Program OTP Register
00C0h
Register Data
9.8.7
Locking the 128-bit OTP Protection Register
The user-programmable segment of the PR is lockable by programming Bit 1 of the
Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to 0 at the
Numonyx factory to protect the unique device number. Bit 1 is set using the Protection
Program command to program “0xFFFD” to the PLR. After these bits have been
programmed, no further changes can be made to the values stored in the Protection
Register. Protection Program commands to a locked section will result in a Status
Register error (SR.4 and SR.1 will be set). The PR lockout state is not reversible.
Table 30: Programming Protection Lock Register Command Bus-Cycles
First Bus Cycle
Second Bus Cycle
Command
Address Bus
Device Address
Data Bus
Address Bus
Data Bus
Program OTP Register
00C0h
80h
FFFDh
Figure 15: 128-bit Protection Register Memory Map
128-Mbit: A[23:1]
64-Mbit: A[22:1]
32-Mbit: A[21:1]
Word Address
128-Bit Protection Register
0x88
0x87
0x86
0x85
0x84
64- bit Segment
( User- Programmable)
0x83
0x82
0x81
64- bit Segment
( Factory- Programmed)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x80
Protection Lock Register
Note: A0 is not used in x16 mode when accessing the protection register map. See Table 31 for x16 addressing. In x8 mode
A0 is used, see Table 32 for x8 addressing.
Datasheet
44
Jan 2011
208032-03
MICRON [ MICRON TECHNOLOGY ]
