Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
4.2
56-Lead TSOP Package Pinout for 32-, 64-,128-Mbit
Figure 6: 56-Lead TSOP Package Pinout (32/64/128 Mbit)
(3)
(5)
A22
CE1
A21
A20
A19
A18
A17
A16
VCC(1)
A15
A14
A13
A12
CE0
VPEN
RP#
A11
A10
A9
56
55
54
1
2
A24
WE#
OE#
STS
DQ15
DQ7
3
53
52
4
5
51
6
50
49
48
47
46
7
DQ14
DQ6
8
9
VSS
DQ13
DQ5
10
Numonyx® Embedded Flash Memory J3
11
12
13
45
44
43
DQ12
DQ4
14
VCCQ
VSS
DQ11
DQ3
56-Lead TSOP Package
42
41
40
39
15
16
17
18
14 mm x 20 mm
Top View
DQ10
DQ2
38
19
A8
37
36
20
21
22
VCC
DQ9
VSS
A7
35
DQ1
A6
34
33
32
31
23
24
25
26
DQ8
A5
DQ0
A0(2)
A4
A3
BYTE#
(4)
A2
30
29
27
28
A23
A1
CE2
Notes:
1.
2.
3.
4.
5.
No internal connection for pin 9; it may be driven or floated. For legacy designs, the pin can be tied to VCC
.
A0 is the least significant address bit.
A22 is valid for 64-Mbit density and above. On 32-Mbit, it is a no-connect (NC).
A23 is valid for 128-Mbit density. On 32- and 64-Mbit, it is a no-connect (NC).
A24 is a no connect (NC) on 128-, 64-, 32- Mbit, reserved for 256-Mbit.
Jan 2011
208032-03
Datasheet
17
MICRON [ MICRON TECHNOLOGY ]
