512Mb, 1Gb, 2Gb: P30-65nm
AC Read Specifications
AC Read Specifications
Table 39: AC Read Specifications
Parameter
Symbol
Min
Max
Unit
Notes
Asynchronous Specifications
READ cycle time
tAVAV
tAVQV
tELQV
Easy BGA
512Mb/1Gb
2Gb
100
–
–
ns
–
105
110
–
TSOP
512Mb/1Gb
512Mb/1Gb
2Gb
–
Address to output valid
CE# LOW to output valid
Easy BGA
100
105
110
100
105
110
25
150
–
ns
ns
–
–
–
TSOP
512Mb/1Gb
512Mb/1Gb
2Gb
–
Easy BGA
–
–
TSOP
512Mb/1Gb
–
ns
ns
ns
ns
ns
ns
ns
ns
–
1, 2
1
OE# LOW to output valid
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
-
RST# HIGH to output valid
CE# LOW to output in Low-Z
OE# LOW to output in Low-Z
CE# HIGH to output in High-Z
OE# HIGH to output in High-Z
-
0
1, 3
1, 2, 3
1, 3
0
–
–
20
15
–
–
Output hold from first occur-
ring address, CE#, or OE#
change
0
CE# pulse width HIGH
tEHEL
tELTV
tEHTZ
tGLTV
tGLTX
tGHTZ
17
–
–
ns
ns
ns
ns
ns
ns
1
CE# LOW to WAIT valid
CE# HIGH to WAIT High-Z
OE# LOW to WAIT valid
OE# LOW to WAIT in Low-Z
OE# HIGH to WAIT in High-Z
17
20
17
–
–
1, 3
1
–
0
–
1, 3
20
Latching Specifications (Easy BGA)
Address setup to ADV# HIGH
CE# LOW to ADV# HIGH
tAVVH
tELVH
tVLQV
10
10
–
–
–
ns
ns
ns
1
ADV# LOW to output valid
Easy BGA
TSOP
512Mb/1Gb
2Gb
100
105
110
–
–
512Mb/1Gb
–
ns
ns
ns
ns
ns
ns
ADV# pulse width LOW
tVLVH
tVHVL
tVHAX
tAPA
10
10
9
ADV# pulse width HIGH
–
Address hold from ADV# HIGH
Page address access
–
1, 4
1
–
25
-
RST# HIGH to ADV# HIGH
Clock Specifications (Easy BGA)
tPHVH
30
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
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