512Mb, 1Gb, 2Gb: P30-65nm
Power and Reset Specifications
Figure 23: Reset Operation Waveforms
tPLPH
tPLRH
tPHQV
VIH
VIL
(A) Reset during
RST#
read mode
Abort
tPHQV
complete
VIH
VIL
(B) Reset during
RST#
RST#
program or block erase
≤
P1 P2
tPLRH
tPHQV
Abort
complete
VIH
VIL
(C) Reset during
program or block erase
≥
P1 P2
tVCCPH
(D) V power-up to
VCC
0V
CC
V
CC
RST# HIGH
Power Supply Decoupling
The device requires careful power supply de-coupling. Three basic power supply cur-
rent considerations are 1) standby current levels, 2) active current levels, and 3) transi-
ent peaks produced when CE# and OE# are asserted and de-asserted.
When the device is accessed, internal conditions change. Circuits within the device ena-
ble charge pumps, and internal logic states change at high speed. These internal activi-
ties produce transient signals. Transient current magnitudes depend on the device out-
puts’ capacitive and inductive loading. Two-line control and correct de-coupling capac-
itor selection suppress transient voltage peaks.
Because the devices draw their power from VCC, VPP, and VCCQ, each power connection
should have a 0.1µF and a 0.01µF ceramic capacitor to ground. High-frequency, inher-
ently low-inductance capacitors should be placed as close as possible to package leads.
Additionally, for every eight devices used in the system, a 4.7µF electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is
meant to overcome voltage droop caused by PCB trace inductance.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
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