256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Write Specifications
Figure 39: Synchronous Read to Write Timing
tAVCH
Latency count
tVLCH tCHAX
CLK
tAVQV
tAVVH
tWHAV
tAVWH
A
tVHVL
tVHAX
tELVH
tVLVH
tEHEL
ADV#
tELCH
tELQV
tEHTZ
tWHEH
CE#
tGHQZ
tGLQV
OE#
tVHWL
tCHWL
tVLWH
tVHWL
tWHAX
tWLWH
tCHWL
tELWL
tWHWL
WE#
tGLTX
tCHTV
WAIT
tCHTX
tCHQX
tCHQV
tWHDX
tGLQX
DQ
Q
D
D
1. WAIT shown de-asserted and High-Z per OE# de-assertion during WRITE operation
(RCR10 = 0, WAIT asserted LOW). Clock is ignored during WRITE operation.
Note:
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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