256Mb and 512Mb (256Mb/256Mb), P30-65nm
Common Flash Interface
Table 30: Burst Read Information (Continued)
Hex Offset
Hex
Code
ASCII Value
(DQ[7:0])
P = 10Ah
Length
Description
Address
1
Number of synchronous mode read configuration
128:
- -04
(P+1E)h
fields that follow. 00h indicates no burst capabili-
ty.
4
1
Synchronous mode read capability configuration
1:
129:
- -01
Bits 3 - 7 = Reserved.
Bits 0 - 2 = n where 2n+1 hex value represents the
maximum number of continuous synchronous
reads when the device is configured for its maxi-
mum word width.
A value of 07h indicates that the device is capa-
ble of continuous linear bursts that will output
data until the internal burst counter reaches the
end of the device’s burstable address space.
This fields’s 3-bit value can be written directly to
the Read Configuration Register bits 0 - 2 if the
device is configured for its maximum word width.
See offset 28h for word width to determine the
burst data output width.
(P+1F)h
4
1
1
1
Synchronous mode read capability configuration
2.
12A:
12B:
12C:
- -02
- -03
- -07
8
16
(P+20)h
(P+21)h
(P+22)
Synchronous mode read capability configuration
3.
Synchronous mode read capability configuration
4.
Continued
Table 31: Partition and Block Erase Region Information
Hex Offset
P = 10Ah
Address
Bottom
12D:
Description
Optional Flash features and commands
Bottom
Top
Length
Top
(P+23)h
(P+23)h
Number of device hardware-partition regions
within the device:
1
12D:
x = 0: a single hardware partition device (no
fields follow).
x specifies the number of device partition regions
containing one or more contiguous erase block
regions
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
62
© 2013 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
