256Mb and 512Mb (256Mb/256Mb), P30-65nm
Program Operation
Program Operation
The device supports three programming methods: Word Programming (40h or 10h),
Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h,
D0h). See Device Command Codes for details on the various programming commands
issued to the device. The following sections describe device programming in detail.
Successful programming requires the addressed block to be unlocked. If the block is
locked down, WP# must be de-asserted and the block must be unlocked before at-
tempting to program the block. Attempting to program a locked block causes a program
error (SR.4 and SR.1 set) and termination of the operation. See Security Modes for de-
tails on locking and unlocking blocks.
Word Programming
Word programming operations are initiated by writing the Word Program Setup com-
mand to the device (see the Command Codes and Definitions table). This is followed by
a second write to the device with the address and data to be programmed. The device
outputs status register data when read (see the Word Program Flowchart). VPP must be
above VPPLK, and within the specified VPPL min/max values.
During programming, the write state machine (WSM) executes a sequence of internal-
ly-timed events that program the desired data bits at the addressed location, and veri-
fies that the bits are sufficiently programmed. Programming the flash memory array
changes 1s to 0s. Memory array bits that are 0s can be changed to 1s only by erasing the
block (see Erase Operations).
The Status Register can be examined for programming progress and errors by reading at
any address. The device remains in the read status register state until another com-
mand is written to the device.
Status Register bit SR.7 indicates the programming status while the sequence executes.
Commands that can be issued to the device during programming are Program Suspend,
Read Status Register, Read Device Identifier, Read CFI, and Read Array (this returns un-
known data).
When programming has finished, status register bit SR.4 (when set) indicates a pro-
gramming failure. If SR.3 is set, the WSM could not perform the word programming op-
eration because VPP was outside of its acceptable limits. If SR.1 is set, the word pro-
gramming operation attempted to program a locked block, causing the operation to
abort.
Before issuing a new command, the status register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow,
when word programming has completed.
Buffered Programming
The device features a 512-word buffer to enable optimum programming performance.
For Buffered Programming, data is first written to an on-chip write buffer. Then the buf-
fer data is programmed into the flash memory array in buffer-size increments. This can
improve system programming performance significantly over non-buffered program-
ming.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. A 1/13 EN
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