256Mb and 512Mb (256Mb/256Mb), P30-65nm
Program Operation
When the Buffered Programming Setup command is issued, Status Register information
is updated and reflects the availability of the buffer. SR.7 indicates buffer availability: if
set, the buffer is available; if cleared, the buffer is not available.
Note: The device default state is to output SR data after the Buffer Programming Setup
Command. CE# and OE# low drive device to update Status Register. It is not allowed to
issue 70h to read SR data after E8h command otherwise 70h would be counted as Word
Count.
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written to
the flash memory array. Subsequent writes provide additional device addresses and da-
ta. All data addresses must lie within the start address plus the word count. Optimum
programming performance and lower power usage are obtained by aligning the starting
address at the beginning of a 512-word boundary (A[9:1] = 0x00 for Easy BGA and TSOP,
A[8:0] for QUAD+ package). The maximum buffer size would be 256-word if the mis-
aligned address range is crossing a 512-word boundary during programming.
After the last data is written to the buffer, the Buffered Programming Confirm command
must be issued to the original block address. The WSM begins to program buffer con-
tents to the flash memory array. If a command other than the Buffered Programming
Confirm command is written to the device, a command sequence error occurs and Sta-
tus Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device
stops programming, and Status Register bits SR[7,4] are set, indicating a programming
failure.
When Buffered Programming has completed, additional buffer writes can be initiated
by issuing another Buffered Programming Setup command and repeating the buffered
program sequence. Buffered programming may be performed with VPP = VPPL or VPPH
(see Operating Conditions for limitations when operating the device with VPP = VPPH).
If an attempt is made to program past an erase-block boundary using the Buffered Pro-
gram command, the device aborts the operation. This generates a command sequence
error, and Status Register bits SR[5,4] are set.
If Buffered programming is attempted while VPP is at or below VPPLK, Status Register bits
SR[4,3] are set. If any errors are detected that have set Status Register bits, the Status
Register should be cleared using the Clear Status Register command.
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up multilevel cell (MLC) flash
programming. The enhanced programming algorithm used in BEFP eliminates tradi-
tional programming elements that drive up overhead in device programmer systems.
BEFP consists of three phases: Setup, Program/Verify, and Exit (see the BEFP Flow-
chart). It uses a write buffer to spread MLC program performance across 512 data
words. Verification occurs in the same phase as programming to accurately program the
flash memory cell to the correct bit state.
A single two-cycle command sequence programs the entire block of data. This en-
hancement eliminates three write cycles per buffer: two commands and the word count
for each set of 512 data words. Host programmer bus cycles fill the device write buffer
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. A 1/13 EN
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