256Mb and 512Mb (256Mb/256Mb), P30-65nm
Program Operation
followed by a status check. SR.0 indicates when data from the buffer has been program-
med into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the write state machine
(WSM) increments internal addressing to automatically select the next 512-word array
boundary. This aspect of BEFP saves host programming equipment the address bus set-
up overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s in-
ternal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
BEFP Requirements and Considerations
Table 14: BEFP Requirements
Parameter/Issue
Case Temperature
VCC
Requirement
Notes
TC = 30°C ± 10 °C
Nominal VCC
VPP
Driven to VPPH
Setup and Confirm
Programming
Target block must be unlocked before issuing the BEFP Setup and Confirm commands.
The first-word address (WA0) of the block to be programmed must be held constant
from the setup phase through all data streaming into the target block, until transition
to the exit phase is desired.
Buffer Alignment
WA0 must align with the start of an array buffer boundary.
1
1. Word buffer boundaries in the array are determined by A[9:1] for Easy BGA and TSOP;
A[8:0] for QUAD+ package (0x000 through 0x1FF). The alignment start point is A[9:1] =
0x000 for Easy BGA and TSOP; A[8:0] = 0x000 for QUAD+ package.
Note:
Table 15: BEFP Considerations
Parameter/Issue
Requirement
Notes
Cycling
For optimum performance, cycling must be limited below 50 erase cycles per block.
1
2
Programming blocks BEFP programs one block at a time; all buffer data must fall within a single block.
Suspend
BEFP cannot be suspended.
Programming the
flash memory array
Programming to the flash memory array can occur only when the buffer is full.
3
1. Some degradation in performance may occur if this limit is exceeded, but the internal
algorithm continues to work properly.
Notes:
2. If the internal address counter increments beyond the block's maximum address, ad-
dressing wraps around to the beginning of the block.
3. If the number of words is less than 512, remaining locations must be filled with 0xFFFF.
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit SR.
7 (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A de-
lay before checking SR.7 is required to allow the WSM enough time to perform all of its
setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR.4 is set
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