256Mb and 512Mb (256Mb/256Mb), P30-65nm
Power-Up and Power-Down
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise,
VCC should attain VCCmin before applying VCCQ and VPP. Device inputs should not be
driven before supply voltage = VCCmin
.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase devi-
ces because systems typically expect to read from flash memory when coming out of re-
set. If a CPU reset occurs without a flash memory reset, proper CPU initialization may
not occur. This is because the flash memory may be providing status information, in-
stead of array data as expected. Connect RST# to the same active low reset signal used
for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memo-
ry protection.
Table 38: Power and Reset
Number
Symbol Parameter
tPLPH RST# pulse width low
tPLRH
Min
100
-
Max
Unit
ns
Notes
P1
P2
-
1, 2, 3, 4
1, 3, 4, 7
1, 3, 4, 7
1, 4, 5, 6
RST# low to device reset during erase
RST# low to device reset during program
VCC Power valid to RST# de-assertion (high)
25
25
-
us
-
P3
tVCCPH
300
1. These specifications are valid for all device versions (packages and speeds).
2. The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed.
3. Not applicable if RST# is tied to Vcc.
Notes:
4. Sampled, but not 100% tested.
5. When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC
VCCMIN
6. When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC
VCCMIN
≥
.
≥
.
7. Reset completes within tPLPH if RST# is asserted while no erase or program operation is
executing.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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