256Mb and 512Mb (256Mb/256Mb), P30-65nm
Flowcharts
Figure 22: Erase Suspend/Resume Procedure
=
SR.6
Start
0
Erase
Completed
1 = Suspended
0 = Completed
Read Status
1
Write 70h
Any Address
Read
Program
Erase Suspend
Read/Program?
(FFh/40h)
Write B0h
Any Address
Read Array Data from
a block other than the
one being erased
Program Loop: to a
block other than the
one being erased
No
Done?
Address = X
Read Status Register
Toggle CE#/OE# to
update the
status register
Yes
Erase Resume
=
SR.7
0
1 = Ready
0 = Busy
Read Array
Write D0h
Any Address
1
Write FFh
1
Erase
Resumed
Read Array
Data
Read Status
Write 70h
Any Address
1. The tERS/SUSP timing between the initial block erase or erase resume command and a
subsequent erase suspend command should be followed.
Note:
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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