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PIC32MX795F512L-80IPT 参数 Datasheet PDF下载

PIC32MX795F512L-80IPT图片预览
型号: PIC32MX795F512L-80IPT
PDF下载: 下载PDF文件 查看货源
内容描述: PIC32闪存编程规范 [PIC32 Flash Programming Specification]
分类和应用: 闪存
文件页数/大小: 68 页 / 1216 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC32  
TABLE 19-2: MTAP_COMMANDDRCOMMANDS  
Command  
MCHP_STATUS  
Value  
Description  
8’h0x00  
8’h0xD1  
8’h0xD0  
NOPand return Status.  
MCHP_ASSERT_RST  
Requests the reset controller to assert device Reset.  
MCHP_DE_ASSERT_RST  
Removes the request for device Reset, which causes the reset  
controller to de-assert device Reset if there is no other source  
requesting Reset (i.e., MCLR).  
MCHP_ERASE  
8’h0xFC  
8’h0xFE  
8’h0xFD  
Cause the Flash controller to perform a Chip Erase.  
MCHP_FLASH_ENABLE(1)  
MCHP_FLASH_DISABLE(1)  
Enables fetches and loads to the Flash (from the processor).  
Disables fetches and loads to the Flash (from the processor).  
Note 1: This command is not required for PIC32MZ EC family devices.  
TABLE 19-3: MCHP STATUS VALUE  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Range  
NVMERR(1)  
0
CFGRDY  
FCBUSY  
FAEN(2)  
DEVRST  
7:0  
CPS  
0
bit 7  
CPS: Code-Protect State bit  
1= Device is not code-protected  
0= Device is code-protected  
bit 6  
bit 5  
Unimplemented: Read as ‘0’  
NVMERR: NVMCON Status bit(1)  
1= An Error occurred during NVM operation  
0= An Error did not occur during NVM operation  
bit 4  
bit 3  
Unimplemented: Read as ‘0’  
CFGRDY: Code-Protect State bit  
1= Configuration has been read and CP is valid  
0= Configuration has not been read  
bit 2  
bit 1  
FCBUSY: Flash Controller Busy bit  
1= Flash controller is busy (Erase is in progress)  
0= Flash controller is not busy (either erase has not started or it has finished)  
FAEN: Flash Access Enable bit(2)  
This bit reflects the state of CFGCON.FAEN.  
1= Flash access is enabled  
0= Flash access is disabled (i.e., processor accesses are blocked)  
bit 0  
DEVRST: Device Reset State bit  
1= Device Reset is active  
0= Device Reset is not active  
Note 1: This bit is not implemented in PIC32MX320/340/360/420/440/460 devices.  
2: This bit is not implemented in PIC32MZ EC family devices.  
TABLE 19-4: EJTAG TAP INSTRUCTIONS  
Command  
ETAP_ADDRESS  
Value  
Description  
5’h0x08  
5’h0x09  
5’h0x0A  
5’h0x0C  
5’h0x0E  
Select Address register.  
Select Data register.  
ETAP_DATA  
ETAP_CONTROL  
ETAP_EJTAGBOOT  
ETAP_FASTDATA  
Select EJTAG Control register.  
Set EjtagBrk, ProbEn and ProbTrap to ‘1’ as the reset value.  
Selects the Data and Fastdata registers.  
DS61145L-page 56  
2007-2013 Microchip Technology Inc.  
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